--CAR_pack.vhd

library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;

package Enum_State_Encode_Types is
	attribute Enum_State_Type_Encoding :string;
	type STATE_TYPE is
		(Stop, Slow, Medium, Fast);
	attribute Enum_State_Type_Encoding of STATE_TYPE: type is
		("11 10 01 00");
end;

--Car_002_FSM.vhd

library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
use work.Enum_State_Encode_Types.all;

entity FSM_CAR_SPEED_CNTL is
	port (Clock, Keys, Brake, Accelerate: in std_logic;
		Speed:out STATE_TYPE);
end;-- entity  FSM_CAR_SPEED_CNTL;

architecture RTL of FSM_CAR_SPEED_CNTL is
	signal   NextSpeed :STATE_TYPE;
	signal   Speed_s   :STATE_TYPE;
begin
	
	FSM2_COMB:process(Keys, Brake, Accelerate, Speed_s, NextSpeed)
	begin
	--		"Speed_s" este un semnal intern care porteaza semnalul "Speed",
	--astfel incat "Speed" sa ramana de tip "out"
		case Speed_s is
			when Stop =>
				if (Accelerate='1') then
					NextSpeed <= Slow;
				else
					NextSpeed <= Stop;
				end if;
			when Slow =>
				if (Brake='1') then
					NextSpeed <= Stop;
				elsif (Accelerate='1') then
					NextSpeed <= Medium;
				else 
					NextSpeed <= Slow;
				end if;
			when Medium =>
				if (Brake='1') then
					NextSpeed <= Slow;
				elsif (Accelerate='1') then
					NextSpeed <= Fast;
				else 
					NextSpeed <= Medium;
				end if;
			when Fast =>
				if (Brake='1') then
					NextSpeed <= Medium;
				else
					NextSpeed <= Fast;
				end if;
			when others =>
					NextSpeed <= Stop;
		end case;
	end process FSM2_COMB;

	FSM2_SEQ: process (Clock,Keys)
	begin
		if (Keys='0') then
			Speed_s <= Stop;
		elsif falling_edge(Clock) then
			Speed_s <= NextSpeed;
		end if;
		Speed <= Speed_s;
	end process FSM2_SEQ;

end; -- architecture RTL;