-- Car_Test.vhd
-----------------------------------------------------------------
-- Modulul generator de clock:

library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;

entity Clock_Gen is
	port (Clock: out std_logic);
end Clock_Gen;

architecture SPEC of Clock_Gen is
	constant clk_prd: time := 200 ns;
	signal   int_clk: std_logic := '0';

begin
	int_clk <= not int_clk after clk_prd/2;
	Clock <= int_clk;
end SPEC;

-----------------------------------------------------------------
-- Generarea semnalelor de test pentru CAR_SPEED_CONTROLER:

library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
use work.Enum_State_Encode_Types.all;

entity FSM_CAR_Control is
		port (Speed: in STATE_TYPE;
			Clock, Keys, Brake, Accelerate: out std_logic);
end FSM_CAR_Control;

architecture DRV of FSM_CAR_Control is
	constant clk_prd: time := 200 ns;
	signal Clock_in, Keys_in, Brake_in, Accelerate_in: std_logic;
	signal CountStop, CountSlow, CountMedium, CountFast: STATE_TYPE := Stop;

component Clock_Gen
	port (Clock: out std_logic);
end component;

begin

	Sursa: Clock_Gen		port map (Clock => Clock_in);

	process
	begin

		Keys_in <= '0' after clk_prd/2,'1' after 2*clk_prd, '0' after 14*clk_prd;
		Brake_in <= '0' after clk_prd/2, '1' after 4*clk_prd, '0' after 6*clk_prd, '1' after 11*clk_prd, '0' after 14*clk_prd;
		Accelerate_in <= '0' after clk_prd/2, '1' after clk_prd, '0' after 5*clk_prd, '1' after 7*clk_prd, '0' after 10*clk_prd;

		wait for 15*clk_prd;

	end process;

	Accelerate <= Accelerate_in;
	Brake <= Brake_in;
	Keys <= Keys_in;
	Clock <= Clock_in;

end DRV;

-----------------------------------------------------------------
-- CAR TEST BENCH:
-- Este autoconsistent si contine modulul CAR_SPEED_CONTROLER
--   si modulul ce genereaza semnalele de test pentru acesta.

library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
use work.Enum_State_Encode_Types.all;

entity Car_Test_Bench is
end Car_Test_Bench;

architecture STRUCT of Car_Test_Bench is
	signal Clock: STD_Logic;
	signal Keys, Brake, Accelerate: STD_Logic;
	signal Speed : STATE_TYPE;

	component FSM_CAR_SPEED_CNTL
		port(   Clock, Keys, Brake, Accelerate: in std_logic;
			Speed:out STATE_TYPE);
	end component;	

	component FSM_CAR_Control
		port (  Speed: in STATE_TYPE;
			Clock, Keys, Brake, Accelerate: out std_logic);
	end component;	

begin
	Car: FSM_CAR_SPEED_CNTL
		port map (Clock => Clock,
			  Keys => Keys,
			  Brake => Brake,
			  Accelerate => Accelerate,
			  Speed => Speed);
	Driver: FSM_CAR_Control
		port map (Speed => Speed,
			  Clock => Clock,
			  Keys => Keys,
			  Brake => Brake,
			  Accelerate => Accelerate);
end STRUCT;