library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
	port (Preset: in Bit;
	        Clear: in Bit;
	        Clock: in Bit;
                        Data: in Bit;
	        Q: out Bit;
	        QBar: out Bit);
end DFF;
architecture Dataflow of DFF is
	signal  A ,B ,C ,D: Bit;
	signal QInt, QBarInt: Bit;
begin
	A<= not (Preset and D and B) after 1 ns;
	B <= not (A and Clear and Clock) after 1 ns;
	C<= not (B and Clock and D) after 1 ns;
	D<= not ( C and Clear and Data) after  1 ns;
	
	QInt <= not (Preset and B and QBarInt ) after 1 ns;
	QBarInt <= not (QInt and Clear and C) after 1 ns;

	Q <= QInt;
	QBar <= QBarInt;
end;