library IEEE;
use IEEE.std_logic_1164.all;

entity Controller is
	port ( STB, CLK, LSB, Stop : in Bit ;
	         Init, Shift, Add , done : out Bit );
end Controller;

architecture FSM of Controller is
	type States  is ( InitS, Checks, AddS, ShiftS, EndS );
	signal State : StateS := EndS ;

begin
-- Drive control outputs based upon State--
	Init <= '1' when State = InitS else '0' ;
	Add <= '1' when State = Adds else '0' ;
	Shift <= '1' when State = ShiftS else '0' ;
	Done <= '1' when State = EndS else '0' ;
-- Determine Next State from control inputs--
StateMachine :
	process (CLK)
	begin
		if CLK'Event and CLK = '0' then
			case State is
				when Inits =>
					State <= Checks;
				when Checks  =>
					if LSB = '1' then
						State <=  AddS ;
					elsif Stop = '0' then 
						State <= ShiftS;
					else
						State <= EndS;
					end if;
				when Adds =>
					State <= Shifts;
				when ShiftS => 
					State <= Checks;
				when Ends =>
					if STB = '1' then 
						State <= InitS ;
					end if;
			end case;
		end if;
	end process;
end;