-- FSM cu cod separat pentru blocurile 
-- NS, CS si OL
library ieee;
use ieee.std_logic_1164.all;

entity FSM_A is
   port(Clk, Reset: in std_logic;
	Ctrl: in std_logic;
	Y: out std_logic_vector(2 downto 0));
end entity FSM_A;

architecture RTL of FSM_A is
  type StateType is (ST1, ST2, ST3, ST4);
  signal CurrentState, NextState: StateType;
begin
  -- blocul next state (NS)
  COMB_NS: process (Ctrl, CurrentState)
  begin
    case CurrentState is
      when ST1 => 
        NextState <= ST2;
      when ST2 =>
        if (Ctrl = '1') then 
          NextState <= ST4;
	else
	  NextState <= ST3;
	end if;
      when ST3 => 
        NextState <= ST4;
      when ST4 => 
        NextState <= ST1;
      when others => 
        NextState <= ST1;
    end case;
  end process COMB_NS;
  
  -- blocul current state (CS)
  SEQ_CS: process (Clk, Reset)
  begin
    if (Reset = '1') then 
      CurrentState <= ST1;
    elsif Clk'event and Clk='1' then
      CurrentState <= NextState;
    end if;
  end process SEQ_CS;

  -- blocul output logic (OL)
  with CurrentState select
    Y <= "001" when ST1,
    	 "010" when ST2,
	 "011" when ST3,
	 "100" when ST4,
	 "001" when others;
end architecture RTL;