-- FSM cu cod combinat pentru blocurile 
-- CS si NS si separat pentru OL
library ieee;
use ieee.std_logic_1164.all;

entity FSM_B is
   port(Clk, Reset: in std_logic;
	Ctrl: in std_logic;
	Y: out std_logic_vector(2 downto 0));
end entity FSM_B;

architecture RTL of FSM_B is
  type StateType is (ST1, ST2, ST3, ST4);
  signal State: StateType;
begin

  -- blocurile NS si CS
  NS_CS: process (Clk, Reset)
  begin
    if (Reset = '1') then 
      State <= ST1;
    elsif Clk'event and Clk='1' then
      case State is
         when ST1 => 
            State <= ST2;
         when ST2 =>
            if (Ctrl = '1') then 
               State <= ST4;
	    else
	       State <= ST3;
	    end if;
         when ST3 => 
            State <= ST4;
         when ST4 => 
            State <= ST1;
         when others => 
            null;
      end case;
    end if;
  end process NS_CS;
  
  -- blocul OL
  with State select
    Y <= "001" when ST1,
    	 "010" when ST2,
	 "011" when ST3,
	 "100" when ST4,
	 "001" when others;
end architecture RTL;