-- FSM cu cod combinat pentru blocurile 
-- NS si OL si separat pentru CS
library ieee;
use ieee.std_logic_1164.all;

entity FSM_C is
   port(Clk, Reset: in std_logic;
	Ctrl: in std_logic;
	Y: out std_logic_vector(2 downto 0));
end entity FSM_C;

architecture RTL of FSM_C is
  type StateType is (ST1, ST2, ST3, ST4);
  signal CurrentState, NextState: StateType;
begin
  
  -- blocurile NS si OL
  COMB_NS_OL: process (Ctrl, CurrentState)
  begin
    case CurrentState is
      when ST1 => 
        Y<="001";
	NextState <= ST2;
      when ST2 =>
        Y<="010";
        if (Ctrl = '1') then 
          NextState <= ST4;
	else
	  NextState <= ST3;
	end if;
      when ST3 =>
        Y<="011"; 
        NextState <= ST4;
      when ST4 =>
        Y<="100"; 
        NextState <= ST1;
      when others =>
        Y<="001"; 
        NextState <= ST1;
    end case;
  end process COMB_NS_OL;

  -- blocul CS
  SEQ_CS: process (Clk, Reset)
  begin
    if (Reset = '1') then 
      CurrentState <= ST1;
    elsif Clk'event and Clk='1' then
      CurrentState <= NextState;
    end if;
  end process SEQ_CS;
  
end architecture RTL;