-- FSM cu cod combinat pentru toate  
-- blocurile NS, CS si OL
library ieee;
use ieee.std_logic_1164.all;

entity FSM_D is
   port(Clk, Reset: in std_logic;
	Ctrl: in std_logic;
	Y: out std_logic_vector(2 downto 0));
end entity FSM_D;

architecture RTL of FSM_D is
begin
  
  -- blocurile CS, NS si OL
  CS_NS_OL: process (Clk, Reset)
    type StateType is (ST1, ST2, ST3, ST4);
    variable State: StateType;
  begin
    if (Reset='1') then
      State := ST1;
    elsif Clk'event and Clk='1' then
       case State is
          when ST1 => 
              State := ST2;
          when ST2 =>
              if (Ctrl = '1') then 
          	 State := ST4;
	      else
	  	 State := ST3;
	      end if;
          when ST3 =>
              State := ST4;
          when ST4 =>
              State := ST1;
          when others =>
              State := ST1;
       end case;
     end if:
     case State is
      when ST1 =>   Y<="001";
	when ST2 =>   Y<="010";
	when ST3 =>   Y<="011";
	when ST4 =>   Y<="100";
	when others=> Y<="001";
     end case;
  end process CS_NS_OL;

end architecture RTL;