library IEEE;
use IEEE.std_logic_1164.all;

entity FullAdder is 
port ( X,Y : in Bit;
         Cin:   in Bit;
         Cout: out Bit;
         Sum: out Bit);
end FullAdder ;

architecture Ecuatii of FullAdder is
begin
	Sum<= X xor Y xor Cin;
	Cout<= (X and Y) or (X and Cin) or (Y and Cin);
end;