library IEEE;
use IEEE.std_logic_1164.all;

entity Mult8 is 
	port ( A, B : in Bit_Vector ( 3 downto 0);
	       Start : in Bit;
	       CLK: in Bit;
               Reset : in Bit;
	       Result : out Bit_Vector ( 7 downto 0);
	       Done : out Bit );
end Mult8;

architecture IterativeAdd of Mult8 is
	use    work.Components.all;
	signal SRAout, SRBout : Bit_Vector (7 downto 0);
	signal ADDout, ACCout : Bit_Vector (7 downto 0);
	signal Init, Shift, Add, Stop : Bit := '0' ;
	signal High : Bit := '1';
	signal Low : Bit := '0';
	signal OFL : Bit;
	signal ACCclk, ACCclr : Bit;
begin
	ACCclr <= not (Init or Reset);  
	ACCclk <= CLK and Add;
	Result <= ACCout;

	SR_A: ShiftN port map
		( CLK => CLK,
		  CLR =>  Low,
		  LD => Init,
		  SH => Shift,
		  DIR =>Low,
		  D => A,
		  Q => SRAout );
	SRB: ShiftN port map
		( CLK => CLK,
		  CLR => Low,
		  LD => Init,
		  SH => Shift,
		  DIR =>High,
		  D => B,
		  Q => SRBout );
	ALU: Adder8 port map
		( ACCout, SRBout, Cin=>Low, Cout=>OFL, Sum=>ADDout);
	ACC: Latch8 port map
		( ADDout, Q=> ACCout, Pre=>High, Clk=>ACCclk, Clr=>ACCclr);
	CHK: Stop <= not ( SRAout(7) or SRAout (6) or SRAout(5) or SRAout (4) or SRAout(3) or SRAout (2) or SRAout(1) or SRAout (0) );
	FSM: Controller port map
		( Start, CLK, SRAout(0), Stop, Init, Shift, Add, Done);
end;