library IEEE;
use IEEE.std_logic_1164.all;

package Components is
	
	component Adder8 
		port ( A,B : in Bit_Vector(7 downto 0);
	 	         Cin: in Bit;
	  	        Cout : out Bit;
	   	        Sum : out Bit_Vector ( 7 downto 0 ));
	end  component ;

	 component Latch8 
		port (D: in Bit_Vector (7 downto 0);
	 	       Clk:in Bit;
	  	       Pre: in Bit;
	   	       Clr: in Bit;
	    	       Q: out Bit_Vector ( 7 downto 0) );
	end component ;

	component ShiftN 
		port ( CLK : in Bit;
	 	         CLR : in Bit;
	  	         LD : in Bit;
	   	        SH : in Bit;
	    	         DIR : in Bit;
	     	         D : in Bit_Vector;
	      	         Q : out Bit_Vector
	         	         );
                end component;

	component Controller 
		port ( STB, CLK, LSB, Stop : in Bit;
                         	          Init, Shift, Add, Done : out Bit );
	end component;

end Components;