library IEEE;
use IEEE.std_logic_1164.all;

entity Test_DFF is end;

architecture Driver of Test_DFF is
	component DFF 
		port (Preset , Clear, Clock, Data: in Bit;
		        Q,QBar:		    out Bit);
	end component;

signal Preset, Clear : Bit :='1';
signal Clock, Data, Q, QBar :Bit;
begin
	UUT: DFF port map (Preset, Clear, Clock, Data, Q, QBar);
Stimulus:
	process
	begin
		Preset <= '0' ; wait for 5 ns;
		Preset <= '1'  ; wait for 5 ns;
		Clear <= '0' ; wait for 5 ns;
		Clear <= '1' ; wait for 5 ns;

		Preset <='0'; Clear  <='0' ; wait for 5 ns;
		Preset <='1' ;Clear <='1' ; wait for 5 ns;

		Clear <= '0' , '1'  after 5 ns; wait for 10 ns;

		Data <= '1'; Clock <= '0' after 1 ns, '1' after 5 ns ;
		wait for 10 ns;
		Data <= '0' ;  Clock <= '0'  after  1  ns, '1' after  5  ns;
		wait for 10 ns;
		-- clear
		Clear <='0', '1' after 5 ns; wait for 10 ns;

		Data <= '0';
		Preset <= '0', '1'   after 10 ns;
		Clock <= '0', '1' after 5 ns; wait for 10 ns;
		-- stop simulation

		wait;

	end process;
end;