library IEEE;
use IEEE.std_logic_1164.all;

entity Test_FullAdder is end;

architecture Driver of Test_FullAdder is
	component FullAdder
	port (X,Y: in Bit;
	        Cin: in Bit;
	         Cout: out Bit;
	         Sum: out Bit ) ;
end component;
signal  X,Y,Cin,Cout,Sum:Bit;

begin
UUT: FullAdder port map (X,Y,Cin,Cout,Sum);
Stimulus:
process 
	type Entry is record
		X,Y,Cin : Bit;
		Cout ,Sum: Bit;
	end record;
	type Table is array ( 0 to 7) of Entry;
	constant TruthTable: Table :=
	(
------------------X----Y-   Cin-  Cout-   Sum
		('0' ,'0', '0',  '0',     '0'),
		('0', '0', '1',  '0',     '1' ),
		('0', '1', '0',  '0',     '1' ),
		('0', '1', '1',  '1',     '0' ),
		('1', '0', '0',  '0',     '1' ),
		('1', '0', '1',  '1',     '0' ),
		('1', '1', '0',  '1',     '0' ),
		('1', '1', '1',  '1',     '1' )
);
begin
	for i in TruthTable'range loop
	X <= TruthTable(i).X;
	Y <= TruthTable(i).Y;
	Cin <= TruthTable(i).Cin;
	wait for 1 ns;
	assert 
		Cout = TruthTable(i) .Cout and 
		Sum = TruthTable(i) .Sum;
end loop;
wait;
end process ;
end;