library IEEE;
use IEEE.std_logic_1164.all;

entity  Test_Latch8 is end ;

architecture Driver of Test_Latch8 is

	component Latch8
		port ( D: in Bit_Vector (7 downto 0);
		        Pre : in Bit;
		        Clr : in Bit;
		        Clk: in Bit;       
                                        Q: out Bit_Vector ( 7 downto 0));
	end component;

	signal D, Q: Bit_Vector (7 downto 0);
	signal Clk, Pre, Clr: Bit := '1' ;

begin
	UUT: Latch8 port map (D, Clk, pre, Clr, Q);
Stimulus:
	process
		variable Temp : Bit_Vector ( 7 downto 0);
begin
	--set the latch--
		Pre <= '0', '1' after 5 ns;
		wait for 10 ns;
	--clear the latch--
		Clr <= '0', '1' after 5 ns;
		wait for 10 ns;
	--load th latch--
	Temp := "00010011";
	for i in 1 to 8 loop
		D <= temp;
		Clk <= '0' after 0 ns,  '1' after 5 ns;
		wait for 10 ns;
		assert Q = Temp report "Load failed";
		Temp := Temp(0) & Temp ( 7 downto 1);
	end loop;
	wait;
	end process;
end;