library IEEE;
use IEEE.std_logic_1164.all;

entity Test_Mult8 is end;

architecture Driver of Test_Mult8 is
	component Mult8 
		port (A,B    : in  Bit_Vector ( 3 downto 0);
		      Start  : in  Bit;	
		      CLK    : in  Bit;
		      Reset  : in  Bit;
		      Result : out Bit_Vector ( 7 downto 0);
		      Done   : out Bit );
	end component;
	signal A,B   : Bit_Vector ( 3 downto 0);
	signal Start, Done : Bit := '0' ;
        signal CLK   : Bit ;
	signal Reset : Bit;
	signal Result: Bit_Vector ( 7 downto 0);
	signal DisplayA, DisplayB, DisplayResult : Natural ;
	use work.Utils.all;
begin
	C:   Clock (CLK, 10 ns, 10 ns);
	UUT: Mult8 port map (A, B, Start, CLK, Reset, Result, Done);
	Reset <= '1' ,'0' after 1 ns;
	Stimulus:
		process
		begin
			for i in 1 to 3 loop 
				for j in 4 to 7 loop
					DisplayA <= i;
					DisplayB <= j;
					A <= Convert ( i, A'Length );
					B <= Convert ( j, B'length);
					wait until CLK'Event and CLK='1';
					Start <='1', '0'  after 20 ns;		
					wait until Done ='1';
					DisplayResult <= Convert (Result);
					wait until CLK'Event and CLK = '1' ;
				end loop;
			end loop;
		wait;
		end process;
end;