library IEEE;
use IEEE.std_logic_1164.all;

entity Test_ShiftN is end;

architecture Driver of Test_ShiftN is
	component ShiftN 
		port ( CLK : in Bit;
		         CLR : in Bit;
	   	         LD : in Bit;
	                         SH : in Bit;
	                         DIR : in Bit;
	                         D : in Bit_Vector;
	                        Q : out Bit_Vector);		
	end component;

	signal CLK, CLR,LD, SH, DIR : Bit ;
	signal D : Bit_Vector ( 1 to 4) ;
	signal Q : Bit_Vector ( 8 downto 1 );
begin
	UUT : ShiftN port map ( CLK, CLR, LD, SH, DIR, D, Q );
	Stimulus:
		process
		begin
--clear the register--
			CLR <= '1' , '0' after 10 ns;
			wait for 10 ns;
--load the register--
			D <= "1110" ;
			LD <= '1' , '0' after 10 ns;
			CLK <= '0' , '1' after 3 ns;
			wait for 10 ns;
-- left shift the pattern
			SH <= '1' ;
			DIR <= '1' ;
			for i in 1 to 5 loop
				Clk <= '0' , '1' after 3 ns;
				wait for 10 ns;
			end loop;
--right shift the pattern
			DIR <= '0' ;
			for i in 1 to 8 loop 
				CLK <= '0' , '1'  after 3 ns;
				wait for 10 ns;
			end loop;
		wait;
		end process;
end;